The invention primarily grew out of needs for making highly reliable, high density dynamic random access memory (DRAM) contacts. Advance semiconductor fabrication is employing increasing vertical circuit integration as designers continue to strive for circuit density maximization. Such typically includes multi-level metallization and interconnect schemes.
Electrical interconnect techniques typically require electrical connection between metal or other conductive layers, or regions, which are present at different elevations within the substrate. Such interconnecting is typically conducted, in part, by etching a contact opening through insulating material to the lower elevation of a layer or conductive region. The significant increase in density of memory cells and vertical integration places very stringent requirements for contact fabrication technology. The increase in circuit density has resulted in narrower and deeper electrical contact openings between layers within the substrate, something commonly referred to as increasing aspect ratio. Such currently ranges from 1.0 to 5, and is expected to increase. Further, the circuit density increase places increasing constraints on the conductivity of the contacts themselves.
As transistor active area dimensions approached one micron in diameter, conventional process parameters resulted in intolerable increased resistance between the active region or area and the conductive layer. The principal way of reducing such contact resistance is by formation of a metal silicide atop the active area prior to application of the conductive film for formation of the conductive runner. One common metal silicide material formed is TiSi.sub.x, where x is predominantly "2". The TiSi.sub.x material is typically provided by first applying a thin layer of titanium atop the wafer which contacts the active areas within the contact openings. Thereafter, the wafer is subjected to a high temperature anneal. This causes the titanium to react with the silicon of the active area, thus forming the TiSi.sub.x. Such a process is said to be self-aligning, as the TiSi.sub.x is only formed where the titanium metal contacts the silicon active regions. The applied titanium film everywhere else overlies an insulative, and substantially non-reactive, SiO.sub.2 layer.
Ultimately, an electrically conductive contact filling material such as tungsten would be provided for making electrical connection to the contact. However, tungsten adheres poorly to TiSi.sub.x. Additionally, it is desirable to prevent intermixing of the contact filling material with the silicide and underlying silicon. Accordingly, an intervening layer is typically provided to prevent the diffusion of the silicon and silicide with the plug filling metal, and to effectively adhere the plug filling metal to the underlying substrate. Such material is, accordingly, also electrically conductive and commonly referred to as a "barrier layer" due to the anti-diffusion properties.
One material of choice for use as a glue/diffusion barrier layer is titanium nitride. TiN is an attractive material as a contact diffusion barrier in silicon integrated circuits because it behaves as an impermeable barrier to silicon, and because the activation energy for the diffusion of other impurities is very high. TiN is also chemically thermodynamically very stable, and it exhibits typical low electrical resistivities of the transition metal carbides, borides, or nitrides.
TiN can be provided or formed on the substrate in one of the following manners: a) by evaporating Ti in an N.sub.2 ambient; b) reactively sputtering Ti in an Ar and N.sub.2 mixture; c) sputtering from a TiN target in an inert (Ar) ambient; d) sputter depositing Ti in an Ar ambient and converting it to TiN in a separate plasma nitridation step; or e) by low pressure chemical vapor deposition.
As device dimensions continue to shrink, adequate step coverage within the contact has become problematic with respect to certain deposition techniques. Chemical vapor deposition (CVD) is known to deposit highly conformal layers, and would be preferable for this reason in depositing into deep, narrow contacts. Yet, adequate contact coverage of electrically conductive materials ultimately placed within deep and narrow contacts continues to challenge the designer in assuring adequate electrical connection between different elevation areas within the substrate.